%0 Conference Paper %1 conf/iscas/IshidaHNA94 %A Ishida, Masaki %A Hayashi, Koichi %A Nishigaki, Masakatsu %A Asai, Hideki %B ISCAS %D 1994 %I IEEE %K dblp %P 411-414 %T Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. %U http://dblp.uni-trier.de/db/conf/iscas/iscas1994-1.html#IshidaHNA94 %@ 0-7803-1916-8

@inproceedings{conf/iscas/IshidaHNA94, added-at = {2016-05-23T00:00:00.000+0200}, author = {Ishida, Masaki and Hayashi, Koichi and Nishigaki, Masakatsu and Asai, Hideki}, biburl = {https://www.bibsonomy.org/bibtex/2ea21f22e74532b146bab6a60e26d44ee/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/1994}, ee = {http://dx.doi.org/10.1109/ISCAS.1994.408826}, interhash = {6d339c9ead7e75c3569098d1fb3b845c}, intrahash = {ea21f22e74532b146bab6a60e26d44ee}, isbn = {0-7803-1916-8}, keywords = {dblp}, pages = {411-414}, publisher = {IEEE}, timestamp = {2016-05-24T11:51:44.000+0200}, title = {Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas1994-1.html#IshidaHNA94}, year = 1994 }