%0 Conference Paper %1 conf/fpga/XuLSL024 %A Xu, Shaoxian %A Lu, Sitong %A Shao, Zhiyuan %A Liao, Xiaofei %A Jin, Hai %B FPGA %D 2024 %E Zhang, Zhiru %E Putnam, Andrew %I ACM %K dblp %P 22-32 %T MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#XuLSL024

@inproceedings{conf/fpga/XuLSL024, added-at = {2024-04-15T00:00:00.000+0200}, author = {Xu, Shaoxian and Lu, Sitong and Shao, Zhiyuan and Liao, Xiaofei and Jin, Hai}, biburl = {https://www.bibsonomy.org/bibtex/26fb5570e2c18bb7f89544178679342e0/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2024}, editor = {Zhang, Zhiru and Putnam, Andrew}, ee = {https://doi.org/10.1145/3626202.3637571}, interhash = {6d6284e204dd85a7afc036d850cc6e21}, intrahash = {6fb5570e2c18bb7f89544178679342e0}, keywords = {dblp}, pages = {22-32}, publisher = {ACM}, timestamp = {2024-04-22T07:46:05.000+0200}, title = {MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#XuLSL024}, year = 2024 }