%0 Journal Article %1 journals/tcad/PomeranzR97 %A Pomeranz, Irith %A Reddy, Sudhakar M. %D 1997 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 5 %P 544-554 %T LOCSTEP: a logic-simulation-based test generation procedure. %U http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#PomeranzR97 %V 16

@article{journals/tcad/PomeranzR97, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/232ebfc7318c1816a4fb04f8f7e99128d/dblp}, ee = {https://doi.org/10.1109/43.631218}, interhash = {6e8b0a74c0327fde26a08d53d1780ef3}, intrahash = {32ebfc7318c1816a4fb04f8f7e99128d}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 5, pages = {544-554}, timestamp = {2020-09-25T11:49:22.000+0200}, title = {LOCSTEP: a logic-simulation-based test generation procedure.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#PomeranzR97}, volume = 16, year = 1997 }