%0 Conference Paper %1 conf/vlsid/BagchiD94 %A Bagchi, Tanuj %A Das, Sajal K. %B VLSI Design %D 1994 %I IEEE Computer Society %K dblp %P 207-210 %T An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1994.html#BagchiD94 %@ 0-8186-4990-9

@inproceedings{conf/vlsid/BagchiD94, added-at = {2023-03-24T00:00:00.000+0100}, author = {Bagchi, Tanuj and Das, Sajal K.}, biburl = {https://www.bibsonomy.org/bibtex/28202ed73f7c441d2556e4edee36a1926/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1994}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1994.282686}, interhash = {6ffbe780dfb2d3078a8e9bb1f0912eb8}, intrahash = {8202ed73f7c441d2556e4edee36a1926}, isbn = {0-8186-4990-9}, keywords = {dblp}, pages = {207-210}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:03.000+0200}, title = {An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1994.html#BagchiD94}, year = 1994 }