%0 Journal Article %1 journals/jssc/LuHY13 %A Lu, Chih-Wen %A Hsiao, Ching-Min %A Yin, Ping-Yeh %D 2013 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1475-1486 %T A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs. %U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#LuHY13 %V 48

@article{journals/jssc/LuHY13, added-at = {2020-08-30T00:00:00.000+0200}, author = {Lu, Chih-Wen and Hsiao, Ching-Min and Yin, Ping-Yeh}, biburl = {https://www.bibsonomy.org/bibtex/28ca45c2e112efceb0978ef19a0fa4596/dblp}, ee = {https://doi.org/10.1109/JSSC.2013.2252525}, interhash = {72d2b046743a69675633796e0aa55f19}, intrahash = {8ca45c2e112efceb0978ef19a0fa4596}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1475-1486}, timestamp = {2020-08-31T11:42:10.000+0200}, title = {A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#LuHY13}, volume = 48, year = 2013 }