%0 Journal Article %1 journals/tcad/YinGLLW16 %A Yin, Shouyi %A Gu, Jiangyuan %A Liu, Dajiang %A Liu, Leibo %A Wei, Shaojun %D 2016 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 9 %P 1475-1488 %T Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. %U http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#YinGLLW16 %V 35

@article{journals/tcad/YinGLLW16, added-at = {2020-09-24T00:00:00.000+0200}, author = {Yin, Shouyi and Gu, Jiangyuan and Liu, Dajiang and Liu, Leibo and Wei, Shaojun}, biburl = {https://www.bibsonomy.org/bibtex/2074c9b92a30382f5a9a861e01b43f0ec/dblp}, ee = {https://doi.org/10.1109/TCAD.2015.2512900}, interhash = {768c0715afc414ec0dc13ee581dc55c6}, intrahash = {074c9b92a30382f5a9a861e01b43f0ec}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 9, pages = {1475-1488}, timestamp = {2020-09-25T11:46:16.000+0200}, title = {Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#YinGLLW16}, volume = 35, year = 2016 }