%0 Generic %1 anu2014design %A Anu, %A Kumar, Amit %A and Neeraj Kr. Shukla, %B Int. Conf. on Recent Trends in Information, Telecommunication and Computing , ITC %D 2014 %I ACEEE (A Computer division of IDES) %K Amplifier Gain Integrator Low Margin Operational Power %T Design and Simulation of High Stability 2-Stage Differential Op-Amp Integrator in 180nm CMOS Technology %X Integrator is an Op-Amp circuit application which does the mathematical operation of integration, i.e. the output voltage is proportional to the integral of i nput voltage. The stability of Op-Amp circuit is analyzed by Gain and Phase Margin curves. This paper also discusses the power consumption of Op-Amp as well as Integrator analog circuit. The circuits are simulated and analyzed at 180nm standard CMOS process. The Gain- Bandwidth product of Operational Amplifier is analyzed at different bias voltages. The power of Integrator is 7.844mW which is evaluated by using the Op-Amp as the lower block of the Integrator. The Unity Gain Bandwidth of Operational Amplifier is 15 MHz at 0.7V biasing voltage and 21 MHz at 0.4V biasing voltage with power consumption of 7.158mW and 6.998mW, respectively

@conference{anu2014design, abstract = { Integrator is an Op-Amp circuit application which does the mathematical operation of integration, i.e. the output voltage is proportional to the integral of i nput voltage. The stability of Op-Amp circuit is analyzed by Gain and Phase Margin curves. This paper also discusses the power consumption of Op-Amp as well as Integrator analog circuit. The circuits are simulated and analyzed at 180nm standard CMOS process. The Gain- Bandwidth product of Operational Amplifier is analyzed at different bias voltages. The power of Integrator is 7.844mW which is evaluated by using the Op-Amp as the lower block of the Integrator. The Unity Gain Bandwidth of Operational Amplifier is 15 MHz at 0.7V biasing voltage and 21 MHz at 0.4V biasing voltage with power consumption of 7.158mW and 6.998mW, respectively}, added-at = {2014-03-21T11:05:56.000+0100}, author = {Anu and Kumar, Amit and and Neeraj Kr. Shukla}, biburl = {https://www.bibsonomy.org/bibtex/28b143c92677f9117bde6dcc2bfa8f5c8/idescitation}, booktitle = {Int. Conf. on Recent Trends in Information, Telecommunication and Computing , ITC}, interhash = {77bea7b816a16120d4137a07ea470ce8}, intrahash = {8b143c92677f9117bde6dcc2bfa8f5c8}, keywords = {Amplifier Gain Integrator Low Margin Operational Power}, organization = {Institute of Doctors Engineers and Scientists}, publisher = {ACEEE (A Computer division of IDES)}, timestamp = {2014-03-21T11:05:56.000+0100}, title = {Design and Simulation of High Stability 2-Stage Differential Op-Amp Integrator in 180nm CMOS Technology }, year = 2014 }