Inproceedings,
Towards an optimised VLSI design algorithm for the constant matrix multiplication problem
Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2006, IEEE, (21-24 May 2006)4 pp., CD-ROM.
DOI: doi:10.1109/ISCAS.2006.1693782
Abstract
The efficient design of multiplierless implementations
of constant matrix multipliers is challenged by the
huge solution search spaces even for small scale
problems. Previous approaches tend to use hill-climbing
algorithms risking sub-optimal results. The proposed
algorithm avoids this by exploring parallel solutions.
The computational complexity is tackled by modelling
the problem in a format amenable to genetic programming
and hardware acceleration. Results show an improvement
on state of the art algorithms with future potential
for even greater savings.
