%0 Conference Paper %1 conf/isvlsi/XydisPSE10 %A Xydis, Sotirios %A Pekmestzi, Kiamal Z. %A Soudris, Dimitrios %A Economakos, George %B ISVLSI %D 2010 %I IEEE Computer Society %K dblp %P 486-487 %T High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2010.html#XydisPSE10 %@ 978-0-7695-4076-4

@inproceedings{conf/isvlsi/XydisPSE10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Xydis, Sotirios and Pekmestzi, Kiamal Z. and Soudris, Dimitrios and Economakos, George}, biburl = {https://www.bibsonomy.org/bibtex/2466621ec5de86ce7d358dbe3e3827249/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2010.8}, interhash = {7d0983d71cc5f26ad2cd4f4ac0e077b6}, intrahash = {466621ec5de86ce7d358dbe3e3827249}, isbn = {978-0-7695-4076-4}, keywords = {dblp}, pages = {486-487}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:07:55.000+0200}, title = {High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2010.html#XydisPSE10}, year = 2010 }