%0 Conference Paper %1 conf/fpl/GoncalvesSG05 %A Gonçalves, Victor %A de Sousa, José T. %A Gonçalves, Fernando M. %B FPL %D 2005 %E Rissa, Tero %E Wilton, Steven J. E. %E Leong, Philip Heng Wai %I IEEE %K dblp %P 481-486 %T A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#GoncalvesSG05 %@ 0-7803-9362-7

@inproceedings{conf/fpl/GoncalvesSG05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Gonçalves, Victor and de Sousa, José T. and Gonçalves, Fernando M.}, biburl = {https://www.bibsonomy.org/bibtex/23cf277b8693e553cb6b0464e316bfe87/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2005}, editor = {Rissa, Tero and Wilton, Steven J. E. and Leong, Philip Heng Wai}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515768}, interhash = {7e346618b57341d0e85221a7b3c1df4e}, intrahash = {3cf277b8693e553cb6b0464e316bfe87}, isbn = {0-7803-9362-7}, keywords = {dblp}, pages = {481-486}, publisher = {IEEE}, timestamp = {2024-04-10T14:52:35.000+0200}, title = {A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#GoncalvesSG05}, year = 2005 }