%0 Conference Paper %1 conf/icecsys/GreenbergBHM04 %A Greenberg, Shlomo %A Bloch, Ido %A Horwitz, Moti %A Maman, Avishay %B ICECS %D 2004 %I IEEE %K dblp %P 419-423 %T Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing. %U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2004.html#GreenbergBHM04 %@ 0-7803-8715-5

@inproceedings{conf/icecsys/GreenbergBHM04, added-at = {2017-05-23T00:00:00.000+0200}, author = {Greenberg, Shlomo and Bloch, Ido and Horwitz, Moti and Maman, Avishay}, biburl = {https://www.bibsonomy.org/bibtex/26abe10e2869f98c53ff2ac9d5ad0adb0/dblp}, booktitle = {ICECS}, crossref = {conf/icecsys/2004}, ee = {https://doi.org/10.1109/ICECS.2004.1399707}, interhash = {7e7231479a1e31441e6a8ce399bdfcce}, intrahash = {6abe10e2869f98c53ff2ac9d5ad0adb0}, isbn = {0-7803-8715-5}, keywords = {dblp}, pages = {419-423}, publisher = {IEEE}, timestamp = {2019-10-17T19:50:21.000+0200}, title = {Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing.}, url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2004.html#GreenbergBHM04}, year = 2004 }