%0 Journal Article %1 journals/jssc/Briseno-Vidrios16 %A Briseno-Vidrios, Carlos %A Edward, Alexander %A Rashidi, Negar %A Silva-Martínez, José %D 2016 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1398-1409 %T A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. %U http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#Briseno-Vidrios16 %V 51

@article{journals/jssc/Briseno-Vidrios16, added-at = {2020-08-30T00:00:00.000+0200}, author = {Briseno-Vidrios, Carlos and Edward, Alexander and Rashidi, Negar and Silva-Martínez, José}, biburl = {https://www.bibsonomy.org/bibtex/2968977c26d702e5b217baed62c7be02a/dblp}, ee = {https://doi.org/10.1109/JSSC.2016.2557809}, interhash = {80c2136d21d6e289226088568ded62c6}, intrahash = {968977c26d702e5b217baed62c7be02a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1398-1409}, timestamp = {2020-08-31T11:44:24.000+0200}, title = {A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#Briseno-Vidrios16}, volume = 51, year = 2016 }