%0 Book %1 stroetmann2007computerarchitektur %A Stroetmann, Karl %C München u.a. %D 2007 %I Oldenbourg %K Techn %T Computer-Architektur : Modellierung, Entwicklung und Verifikation mit Verilog %U http://www.worldcat.org/search?qt=worldcat_org_all&q=3486580299 %@ 9783486580297 3486580299

@book{stroetmann2007computerarchitektur, added-at = {2014-01-13T17:09:11.000+0100}, address = {München [u.a.]}, author = {Stroetmann, Karl}, biburl = {https://www.bibsonomy.org/bibtex/20ca82bf14b69d954bfff0bbf9753d12b/benjamin.ternes}, interhash = {82bb3f0c30a40093e8573c0451689e30}, intrahash = {0ca82bf14b69d954bfff0bbf9753d12b}, isbn = {9783486580297 3486580299}, keywords = {Techn}, publisher = {Oldenbourg}, refid = {162429265}, timestamp = {2014-01-13T17:09:11.000+0100}, title = {Computer-Architektur : Modellierung, Entwicklung und Verifikation mit Verilog}, url = {http://www.worldcat.org/search?qt=worldcat_org_all&q=3486580299}, year = 2007 }