%0 Conference Paper %1 conf/compsac/ZverlovV14 %A Zverlov, Sergey %A Voss, Sebastian %B COMPSAC Workshops %D 2014 %I IEEE Computer Society %K dblp %P 366-371 %T Synthesis of Pareto Efficient Technical Architectures for Multi-core Systems. %U http://dblp.uni-trier.de/db/conf/compsac/compsac2014w.html#ZverlovV14 %@ 978-1-4799-3578-9

@inproceedings{conf/compsac/ZverlovV14, added-at = {2023-03-24T00:00:00.000+0100}, author = {Zverlov, Sergey and Voss, Sebastian}, biburl = {https://www.bibsonomy.org/bibtex/26a2a0bf5ffd55492fedac04c12e116f7/dblp}, booktitle = {COMPSAC Workshops}, crossref = {conf/compsac/2014w}, ee = {https://doi.ieeecomputersociety.org/10.1109/COMPSACW.2014.63}, interhash = {830d752d0ef0eed70ebf1ad43f87b484}, intrahash = {6a2a0bf5ffd55492fedac04c12e116f7}, isbn = {978-1-4799-3578-9}, keywords = {dblp}, pages = {366-371}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:56:09.000+0200}, title = {Synthesis of Pareto Efficient Technical Architectures for Multi-core Systems.}, url = {http://dblp.uni-trier.de/db/conf/compsac/compsac2014w.html#ZverlovV14}, year = 2014 }