%0 Journal Article %1 journals/tcad/VenkataramaniKS20 %A Venkataramani, Swagath %A Kozhikkottu, Vivek Joy %A Sabne, Amit %A Roy, Kaushik %A Raghunathan, Anand %D 2020 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 2503-2515 %T Logic Synthesis of Approximate Circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad39.html#VenkataramaniKS20 %V 39

@article{journals/tcad/VenkataramaniKS20, added-at = {2021-10-14T00:00:00.000+0200}, author = {Venkataramani, Swagath and Kozhikkottu, Vivek Joy and Sabne, Amit and Roy, Kaushik and Raghunathan, Anand}, biburl = {https://www.bibsonomy.org/bibtex/20729c319bc2a41b4cd01d19df49b116f/dblp}, ee = {https://doi.org/10.1109/TCAD.2019.2940680}, interhash = {845a2b85663123ee31087496d70e45c3}, intrahash = {0729c319bc2a41b4cd01d19df49b116f}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {2503-2515}, timestamp = {2024-04-08T19:45:30.000+0200}, title = {Logic Synthesis of Approximate Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad39.html#VenkataramaniKS20}, volume = 39, year = 2020 }