%0 Journal Article %1 journals/tvlsi/ChengP02 %A Cheng, Wei-Chung %A Pedram, Massoud %D 2002 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 2 %P 109-118 %T Power-optimal encoding for a DRAM address bus. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi10.html#ChengP02 %V 10

@article{journals/tvlsi/ChengP02, added-at = {2020-03-11T00:00:00.000+0100}, author = {Cheng, Wei-Chung and Pedram, Massoud}, biburl = {https://www.bibsonomy.org/bibtex/26d3c21ec4c160fc1e12abb94cd29f454/dblp}, ee = {https://doi.org/10.1109/92.994988}, interhash = {85024b1438325bbe1934024a766f6a7a}, intrahash = {6d3c21ec4c160fc1e12abb94cd29f454}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 2, pages = {109-118}, timestamp = {2020-03-12T11:45:40.000+0100}, title = {Power-optimal encoding for a DRAM address bus.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi10.html#ChengP02}, volume = 10, year = 2002 }