%0 Journal Article %1 journals/tvlsi/ZhouZWZYG17 %A Zhou, Jian-Bin %A Zhou, Dajiang %A Wang, Shihao %A Zhang, Shuping %A Yoshimura, Takeshi %A Goto, Satoshi %D 2017 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 2 %P 714-724 %T A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#ZhouZWZYG17 %V 25

@article{journals/tvlsi/ZhouZWZYG17, added-at = {2020-03-11T00:00:00.000+0100}, author = {Zhou, Jian-Bin and Zhou, Dajiang and Wang, Shihao and Zhang, Shuping and Yoshimura, Takeshi and Goto, Satoshi}, biburl = {https://www.bibsonomy.org/bibtex/236168d04ab6a3a9f6dbdce4746118d40/dblp}, ee = {https://doi.org/10.1109/TVLSI.2016.2593581}, interhash = {8c64f3797b5ade8515d6e52369cd8ec1}, intrahash = {36168d04ab6a3a9f6dbdce4746118d40}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 2, pages = {714-724}, timestamp = {2020-03-12T11:45:06.000+0100}, title = {A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#ZhouZWZYG17}, volume = 25, year = 2017 }