%0 Conference Paper %1 conf/vlsid/PomeranzR99 %A Pomeranz, Irith %A Reddy, Sudhakar M. %B VLSI Design %D 1999 %I IEEE Computer Society %K dblp %P 250-255 %T VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1999.html#PomeranzR99 %@ 0-7695-0013-7

@inproceedings{conf/vlsid/PomeranzR99, added-at = {2023-03-24T00:00:00.000+0100}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/29ffc111005deeccc1fc0aa38cac1b905/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1999}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745156}, interhash = {8d51fc97c5073a21b7175070a96427d7}, intrahash = {9ffc111005deeccc1fc0aa38cac1b905}, isbn = {0-7695-0013-7}, keywords = {dblp}, pages = {250-255}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:18.000+0200}, title = {VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1999.html#PomeranzR99}, year = 1999 }