%0 Conference Paper %1 conf/isscc/HaraguchiFYCHCNWC24 %A Haraguchi, Masaru %A Fujino, Yorinobu %A Yokoyama, Yoshisato %A Chang, Ming-Hung %A Hsu, Yu-Hao %A Cheng, Hong-Chen %A Nii, Koji %A Wang, Yih %A Chang, Tsung-Yung Jonathan %B ISSCC %D 2024 %I IEEE %K dblp %P 280-282 %T 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#HaraguchiFYCHCNWC24 %@ 979-8-3503-0620-0

@inproceedings{conf/isscc/HaraguchiFYCHCNWC24, added-at = {2024-05-07T00:00:00.000+0200}, author = {Haraguchi, Masaru and Fujino, Yorinobu and Yokoyama, Yoshisato and Chang, Ming-Hung and Hsu, Yu-Hao and Cheng, Hong-Chen and Nii, Koji and Wang, Yih and Chang, Tsung-Yung Jonathan}, biburl = {https://www.bibsonomy.org/bibtex/2d967ace40ac7368d41eaf1fd9904f203/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2024}, ee = {https://doi.org/10.1109/ISSCC49657.2024.10454463}, interhash = {8d7d78f9362903567d36b6a2b48c6155}, intrahash = {d967ace40ac7368d41eaf1fd9904f203}, isbn = {979-8-3503-0620-0}, keywords = {dblp}, pages = {280-282}, publisher = {IEEE}, timestamp = {2024-05-13T09:02:33.000+0200}, title = {15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#HaraguchiFYCHCNWC24}, year = 2024 }