%0 Conference Paper %1 conf/itc/ThakerAZ00 %A Thaker, Pradip A. %A Agrawal, Vishwani D. %A Zaghloul, Mona E. %B ITC %D 2000 %I IEEE Computer Society %K dblp %P 940-949 %T Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. %U http://dblp.uni-trier.de/db/conf/itc/itc2000.html#ThakerAZ00 %@ 0-7803-6546-1

@inproceedings{conf/itc/ThakerAZ00, added-at = {2023-03-23T00:00:00.000+0100}, author = {Thaker, Pradip A. and Agrawal, Vishwani D. and Zaghloul, Mona E.}, biburl = {https://www.bibsonomy.org/bibtex/23b5532243b5a0ae4e30d3248a07a90a7/dblp}, booktitle = {ITC}, crossref = {conf/itc/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.2000.894305}, interhash = {91406088e65554617e3c31d085285bfc}, intrahash = {3b5532243b5a0ae4e30d3248a07a90a7}, isbn = {0-7803-6546-1}, keywords = {dblp}, pages = {940-949}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:28:46.000+0200}, title = {Register-transfer level fault modeling and test evaluation techniques for VLSI circuits.}, url = {http://dblp.uni-trier.de/db/conf/itc/itc2000.html#ThakerAZ00}, year = 2000 }