%0 Journal Article %1 journals/vlsi/XiaoC14 %A Xiao, Ran %A Chen, Chunhong %D 2014 %J VLSI Design %K dblp %P 529392:1-529392:12 %T Gate-Level Circuit Reliability Analysis: A Survey. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2014.html#XiaoC14 %V 2014

@article{journals/vlsi/XiaoC14, added-at = {2019-06-02T00:00:00.000+0200}, author = {Xiao, Ran and Chen, Chunhong}, biburl = {https://www.bibsonomy.org/bibtex/216a8e9cede912de502455af9fcd9f208/dblp}, ee = {https://www.wikidata.org/entity/Q59101280}, interhash = {966d31656723919b9ff4203334d94753}, intrahash = {16a8e9cede912de502455af9fcd9f208}, journal = {VLSI Design}, keywords = {dblp}, pages = {529392:1-529392:12}, timestamp = {2019-06-04T11:47:18.000+0200}, title = {Gate-Level Circuit Reliability Analysis: A Survey.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2014.html#XiaoC14}, volume = 2014, year = 2014 }