%0 Journal Article %1 journals/jssc/FerrissPNRPTBYVSF13 %A Ferriss, Mark A. %A Plouchart, Jean-Olivier %A Natarajan, Arun %A Rylyakov, Alexander V. %A Parker, Benjamin D. %A Tierno, José A. %A Babakhani, Aydin %A Yaldiz, Soner %A Valdes-Garcia, Alberto %A Sadhu, Bodhisatwa %A Friedman, Daniel J. %D 2013 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 996-1008 %T An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. %U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#FerrissPNRPTBYVSF13 %V 48

@article{journals/jssc/FerrissPNRPTBYVSF13, added-at = {2022-09-02T00:00:00.000+0200}, author = {Ferriss, Mark A. and Plouchart, Jean-Olivier and Natarajan, Arun and Rylyakov, Alexander V. and Parker, Benjamin D. and Tierno, José A. and Babakhani, Aydin and Yaldiz, Soner and Valdes-Garcia, Alberto and Sadhu, Bodhisatwa and Friedman, Daniel J.}, biburl = {https://www.bibsonomy.org/bibtex/2276f103b3fc18330c8844be65232aee9/dblp}, ee = {https://doi.org/10.1109/JSSC.2013.2239114}, interhash = {967ef9897b08b029487d71f98b74a160}, intrahash = {276f103b3fc18330c8844be65232aee9}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {996-1008}, timestamp = {2024-04-08T10:42:14.000+0200}, title = {An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#FerrissPNRPTBYVSF13}, volume = 48, year = 2013 }