%0 Conference Paper %1 conf/fpt/ChenZYN11 %A Chen, Wei %A Zhang, Xiaolin %A Yoshimura, Takeshi %A Nakamura, Yuichi %B FPT %D 2011 %E Tessier, Russell %I IEEE %K dblp %P 1-5 %T A low power technology mapping method for Adaptive Logic Module. %U http://dblp.uni-trier.de/db/conf/fpt/fpt2011.html#ChenZYN11 %@ 978-1-4577-1741-3

@inproceedings{conf/fpt/ChenZYN11, added-at = {2023-03-10T00:00:00.000+0100}, author = {Chen, Wei and Zhang, Xiaolin and Yoshimura, Takeshi and Nakamura, Yuichi}, biburl = {https://www.bibsonomy.org/bibtex/2a69e615d7a4b44400b93ac9cf1422304/dblp}, booktitle = {FPT}, crossref = {conf/fpt/2011}, editor = {Tessier, Russell}, ee = {https://doi.org/10.1109/FPT.2011.6132674}, interhash = {986cb41fe71c49e9476e5c7109c36917}, intrahash = {a69e615d7a4b44400b93ac9cf1422304}, isbn = {978-1-4577-1741-3}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2024-04-10T06:34:16.000+0200}, title = {A low power technology mapping method for Adaptive Logic Module.}, url = {http://dblp.uni-trier.de/db/conf/fpt/fpt2011.html#ChenZYN11}, year = 2011 }