%0 Book %1 hoppe2006verilog %A Hoppe, Bernhard %C München u.a. %D 2006 %I Oldenbourg %K TechnischeInformatik %T Verilog : Modellbildung für Synthese und Verifikation %U http://www.worldcat.org/search?qt=worldcat_org_all&q=3486580043 %@ 3486580043 9783486580044

@book{hoppe2006verilog, added-at = {2014-01-13T17:08:51.000+0100}, address = {München [u.a.}, author = {Hoppe, Bernhard}, biburl = {https://www.bibsonomy.org/bibtex/243f733f2af0134b416bd8d7da7b69189/benjamin.ternes}, interhash = {989afebcaca0fce2b1734185f87faa3c}, intrahash = {43f733f2af0134b416bd8d7da7b69189}, isbn = {3486580043 9783486580044}, keywords = {TechnischeInformatik}, publisher = {Oldenbourg}, refid = {162219609}, timestamp = {2014-01-13T17:08:51.000+0100}, title = {Verilog : Modellbildung für Synthese und Verifikation}, url = {http://www.worldcat.org/search?qt=worldcat_org_all&q=3486580043}, year = 2006 }