%0 Conference Paper %1 conf/vlsid/AgrawalSSD93 %A Agrawal, Aditya %A Srinivas, P. V. %A Sreenivas, Gade %A Dasgupta, Uttiya %B VLSI Design %D 1993 %I IEEE Computer Society %K dblp %P 230-235 %T LATCHECK: A Latchup Checker for VLSI Layouts. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#AgrawalSSD93 %@ 0-8186-3180-5

@inproceedings{conf/vlsid/AgrawalSSD93, added-at = {2023-03-24T00:00:00.000+0100}, author = {Agrawal, Aditya and Srinivas, P. V. and Sreenivas, Gade and Dasgupta, Uttiya}, biburl = {https://www.bibsonomy.org/bibtex/225f17dffd033a94a45bc80788108b024/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1993}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669685}, interhash = {a171c4536f8a166dd5fce29ea051e5b6}, intrahash = {25f17dffd033a94a45bc80788108b024}, isbn = {0-8186-3180-5}, keywords = {dblp}, pages = {230-235}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:57.000+0200}, title = {LATCHECK: A Latchup Checker for VLSI Layouts.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#AgrawalSSD93}, year = 1993 }