%0 Conference Paper %1 conf/vlsid/WilleGDD09 %A Wille, Robert %A Große, Daniel %A Dueck, Gerhard W. %A Drechsler, Rolf %B VLSI Design %D 2009 %I IEEE Computer Society %K %P 189-194 %T Reversible Logic Synthesis with Output Permutation. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#WilleGDD09 %@ 978-0-7695-3506-7

@inproceedings{conf/vlsid/WilleGDD09, added-at = {2023-12-13T05:51:16.000+0100}, author = {Wille, Robert and Große, Daniel and Dueck, Gerhard W. and Drechsler, Rolf}, biburl = {https://www.bibsonomy.org/bibtex/2a4f58a0b712aad8740766cb31257e9f0/admin}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2009}, ee = {https://www.wikidata.org/entity/Q59242688}, interhash = {a752028f650f17581eac03beceda0a57}, intrahash = {a4f58a0b712aad8740766cb31257e9f0}, isbn = {978-0-7695-3506-7}, keywords = {}, pages = {189-194}, publisher = {IEEE Computer Society}, timestamp = {2023-12-13T05:51:16.000+0100}, title = {Reversible Logic Synthesis with Output Permutation.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#WilleGDD09}, year = 2009 }