%0 Journal Article %1 journals/integration/SierraCC19 %A Sierra, Roberto %A Carreras, Carlos %A Caffarena, Gabriel %D 2019 %J Integr. %K dblp %P 1-11 %T Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. %U http://dblp.uni-trier.de/db/journals/integration/integration68.html#SierraCC19 %V 68

@article{journals/integration/SierraCC19, added-at = {2022-01-03T00:00:00.000+0100}, author = {Sierra, Roberto and Carreras, Carlos and Caffarena, Gabriel}, biburl = {https://www.bibsonomy.org/bibtex/28e63439dd5ba213630ec523af9c8237c/dblp}, ee = {https://doi.org/10.1016/j.vlsi.2019.05.001}, interhash = {a89ee0473c14bef2259808e0cfd4a43c}, intrahash = {8e63439dd5ba213630ec523af9c8237c}, journal = {Integr.}, keywords = {dblp}, pages = {1-11}, timestamp = {2024-04-08T13:14:47.000+0200}, title = {Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration68.html#SierraCC19}, volume = 68, year = 2019 }