%0 Conference Paper %1 conf/vlsic/HsuAAKMSKB12 %A Hsu, Steven %A Agarwal, Amit %A Anders, Mark A. %A Kaul, Himanshu %A Mathew, Sanu %A Sheikh, Farhana %A Krishnamurthy, Ram %A Borkar, Shekhar %B VLSIC %D 2012 %I IEEE %K dblp %P 118-119 %T A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#HsuAAKMSKB12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/HsuAAKMSKB12, added-at = {2024-02-05T00:00:00.000+0100}, author = {Hsu, Steven and Agarwal, Amit and Anders, Mark A. and Kaul, Himanshu and Mathew, Sanu and Sheikh, Farhana and Krishnamurthy, Ram and Borkar, Shekhar}, biburl = {https://www.bibsonomy.org/bibtex/2aff407117d69f3111a0f32c10421964f/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {https://doi.org/10.1109/VLSIC.2012.6243818}, interhash = {a8f4808b6d27bb8615763732bc715c66}, intrahash = {aff407117d69f3111a0f32c10421964f}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {118-119}, publisher = {IEEE}, timestamp = {2024-04-10T15:33:47.000+0200}, title = {A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#HsuAAKMSKB12}, year = 2012 }