%0 Journal Article %1 journals/tvlsi/Bank-TavakoliGK20 %A Bank-Tavakoli, Erfan %A Ghasemzadeh, Seyed Abolfazl %A Kamal, Mehdi %A Afzali-Kusha, Ali %A Pedram, Massoud %D 2020 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 838-842 %T POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#Bank-TavakoliGK20 %V 28

@article{journals/tvlsi/Bank-TavakoliGK20, added-at = {2020-10-26T00:00:00.000+0100}, author = {Bank-Tavakoli, Erfan and Ghasemzadeh, Seyed Abolfazl and Kamal, Mehdi and Afzali-Kusha, Ali and Pedram, Massoud}, biburl = {https://www.bibsonomy.org/bibtex/201cae71950096278e0f1eb18166cd2b0/dblp}, ee = {https://doi.org/10.1109/TVLSI.2019.2947639}, interhash = {b2c3e8af80354275caf5188f2563b5c3}, intrahash = {01cae71950096278e0f1eb18166cd2b0}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {838-842}, timestamp = {2020-10-27T11:55:34.000+0100}, title = {POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#Bank-TavakoliGK20}, volume = 28, year = 2020 }