%0 Conference Paper %1 conf/ftcs/JhaPRM92 %A Jha, Niraj K. %A Pomeranz, Irith %A Reddy, Sudhakar M. %A Miller, Robert J. %B FTCS %D 1992 %I IEEE Computer Society %K dblp %P 280-287 %T Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. %U http://dblp.uni-trier.de/db/conf/ftcs/ftcs92.html#JhaPRM92 %@ 0-8186-2875-8

@inproceedings{conf/ftcs/JhaPRM92, added-at = {2017-05-23T00:00:00.000+0200}, author = {Jha, Niraj K. and Pomeranz, Irith and Reddy, Sudhakar M. and Miller, Robert J.}, biburl = {https://www.bibsonomy.org/bibtex/2649d954b96dcd5538a30128b28a32224/dblp}, booktitle = {FTCS}, crossref = {conf/ftcs/1992}, ee = {https://doi.org/10.1109/FTCS.1992.243573}, interhash = {b47515866500221acedbfa8f4bb5480e}, intrahash = {649d954b96dcd5538a30128b28a32224}, isbn = {0-8186-2875-8}, keywords = {dblp}, pages = {280-287}, publisher = {IEEE Computer Society}, timestamp = {2019-10-17T13:30:36.000+0200}, title = {Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.}, url = {http://dblp.uni-trier.de/db/conf/ftcs/ftcs92.html#JhaPRM92}, year = 1992 }