%0 Conference Paper %1 conf/vlsid/ChattopadhyayKN11 %A Chattopadhyay, Biman %A Kamath, Anant S. %A Nayak, Gopalkrishna %B VLSI Design %D 2011 %I IEEE Computer Society %K dblp %P 47-51 %T A 1.8GHz Digital PLL in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2011.html#ChattopadhyayKN11 %@ 978-0-7695-4348-2

@inproceedings{conf/vlsid/ChattopadhyayKN11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Chattopadhyay, Biman and Kamath, Anant S. and Nayak, Gopalkrishna}, biburl = {https://www.bibsonomy.org/bibtex/2c9d09c165bc821f2d869e73f6cc70671/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2011.32}, interhash = {b5d14f448511d0ab2084ce6011b04df3}, intrahash = {c9d09c165bc821f2d869e73f6cc70671}, isbn = {978-0-7695-4348-2}, keywords = {dblp}, pages = {47-51}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:08:33.000+0200}, title = {A 1.8GHz Digital PLL in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2011.html#ChattopadhyayKN11}, year = 2011 }