%0 Journal Article %1 journals/jcsc/LiJHYXDS23 %A Li, Kangle %A Jiang, Lin %A Huang, Xingjie %A Yang, Kun %A Xie, Xiaoyan %A Deng, Junyong %A Shan, Rui %D 2023 %J J. Circuits Syst. Comput. %K dblp %N 9 %P 2350157:1-2350157:27 %T DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc32.html#LiJHYXDS23 %V 32

@article{journals/jcsc/LiJHYXDS23, added-at = {2023-07-07T00:00:00.000+0200}, author = {Li, Kangle and Jiang, Lin and Huang, Xingjie and Yang, Kun and Xie, Xiaoyan and Deng, Junyong and Shan, Rui}, biburl = {https://www.bibsonomy.org/bibtex/2fd69f6ec02a439de12e45660b77b5ce0/dblp}, ee = {https://doi.org/10.1142/S0218126623501578}, interhash = {b74ca51866dd1cdc3b431b11edd65200}, intrahash = {fd69f6ec02a439de12e45660b77b5ce0}, journal = {J. Circuits Syst. Comput.}, keywords = {dblp}, month = {June}, number = 9, pages = {2350157:1-2350157:27}, timestamp = {2024-04-08T19:35:47.000+0200}, title = {DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc32.html#LiJHYXDS23}, volume = 32, year = 2023 }