%0 Journal Article %1 journals/tvlsi/WangMDC09 %A Wang, Hua %A Miranda, Miguel %A Dehaene, Wim %A Catthoor, Francky %D 2009 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 117-127 %T Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#WangMDC09 %V 17

@article{journals/tvlsi/WangMDC09, added-at = {2020-03-11T00:00:00.000+0100}, author = {Wang, Hua and Miranda, Miguel and Dehaene, Wim and Catthoor, Francky}, biburl = {https://www.bibsonomy.org/bibtex/2b07d2e2721181a58d33b4cc1169f496e/dblp}, ee = {https://doi.org/10.1109/TVLSI.2008.2003169}, interhash = {bd1ae0a67acd6e7ee3c10c54fb4d0cbe}, intrahash = {b07d2e2721181a58d33b4cc1169f496e}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {117-127}, timestamp = {2020-03-12T11:42:08.000+0100}, title = {Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#WangMDC09}, volume = 17, year = 2009 }