%0 Conference Paper %1 conf/fpl/IskanderPC11 %A Iskander, Yousef %A Patterson, Cameron D. %A Craven, Stephen D. %B FPL %D 2011 %I IEEE Computer Society %K dblp %P 518-523 %T Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#IskanderPC11 %@ 978-1-4577-1484-9

@inproceedings{conf/fpl/IskanderPC11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Iskander, Yousef and Patterson, Cameron D. and Craven, Stephen D.}, biburl = {https://www.bibsonomy.org/bibtex/236d7168cf40828acc0160453849a8d49/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2011.102}, interhash = {c0c362ee0c87d87ef3ca8711d26d4640}, intrahash = {36d7168cf40828acc0160453849a8d49}, isbn = {978-1-4577-1484-9}, keywords = {dblp}, pages = {518-523}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T14:51:39.000+0200}, title = {Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#IskanderPC11}, year = 2011 }