%0 Journal Article %1 journals/vlsisp/TietcheRD15 %A Tietche, Brunel Happi %A Romain, Olivier %A Denby, Bruce %D 2015 %J J. Signal Process. Syst. %K dblp %N 2 %P 147-154 %T A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp78.html#TietcheRD15 %V 78

@article{journals/vlsisp/TietcheRD15, added-at = {2020-03-12T00:00:00.000+0100}, author = {Tietche, Brunel Happi and Romain, Olivier and Denby, Bruce}, biburl = {https://www.bibsonomy.org/bibtex/24070eceaec2b49242e596a442502d88c/dblp}, ee = {https://www.wikidata.org/entity/Q59403342}, interhash = {c3632701265870c7a01570d012405c12}, intrahash = {4070eceaec2b49242e596a442502d88c}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 2, pages = {147-154}, timestamp = {2020-03-13T12:00:39.000+0100}, title = {A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp78.html#TietcheRD15}, volume = 78, year = 2015 }