%0 Conference Paper %1 conf/apccas/ChingBYR10 %A Ching, Mai Y. %A Boon, Ang T. %A Yeong, Chin K. %A Rokhani, Fakhrul Zaman %B APCCAS %D 2010 %I IEEE %K dblp %P 1143-1146 %T Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2010.html#ChingBYR10 %@ 978-1-4244-7454-7

@inproceedings{conf/apccas/ChingBYR10, added-at = {2014-02-19T00:00:00.000+0100}, author = {Ching, Mai Y. and Boon, Ang T. and Yeong, Chin K. and Rokhani, Fakhrul Zaman}, biburl = {https://www.bibsonomy.org/bibtex/2db0ab0e58e23c4f20895ba9bf24ee92e/dblp}, booktitle = {APCCAS}, crossref = {conf/apccas/2010}, ee = {http://dx.doi.org/10.1109/APCCAS.2010.5775086}, interhash = {c4cd2791bbdf66fdb81f9f248d5ab731}, intrahash = {db0ab0e58e23c4f20895ba9bf24ee92e}, isbn = {978-1-4244-7454-7}, keywords = {dblp}, pages = {1143-1146}, publisher = {IEEE}, timestamp = {2015-06-19T04:15:07.000+0200}, title = {Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2010.html#ChingBYR10}, year = 2010 }