%0 Journal Article %1 journals/ieicet/SaenTK17 %A Saen, Makoto %A Toba, Tadanobu %A Kanno, Yusuke %D 2017 %J IEICE Trans. Electron. %K dblp %N 4 %P 382-390 %T Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet100c.html#SaenTK17 %V 100-C

@article{journals/ieicet/SaenTK17, added-at = {2020-04-11T00:00:00.000+0200}, author = {Saen, Makoto and Toba, Tadanobu and Kanno, Yusuke}, biburl = {https://www.bibsonomy.org/bibtex/2fefc03d0b43905b597028ab9bc77de04/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e100-c_4_382}, interhash = {d9eb827cd3de676a91cdb8ba3d26e516}, intrahash = {fefc03d0b43905b597028ab9bc77de04}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 4, pages = {382-390}, timestamp = {2020-04-14T11:39:39.000+0200}, title = {Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet100c.html#SaenTK17}, volume = {100-C}, year = 2017 }