%0 Conference Paper %1 conf/vlsid/CaputaS06 %A Caputa, Peter %A Svensson, Christer %B VLSI Design %D 2006 %I IEEE Computer Society %K dblp %P 117-122 %T A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#CaputaS06 %@ 0-7695-2502-4

@inproceedings{conf/vlsid/CaputaS06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Caputa, Peter and Svensson, Christer}, biburl = {https://www.bibsonomy.org/bibtex/2a99e8a5b8fbc665f6cb44339a93a6a9e/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.6}, interhash = {dadb2641a24a96079b7a18a141ca284c}, intrahash = {a99e8a5b8fbc665f6cb44339a93a6a9e}, isbn = {0-7695-2502-4}, keywords = {dblp}, pages = {117-122}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:52.000+0200}, title = {A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#CaputaS06}, year = 2006 }