%0 Conference Paper %1 conf/hipeac/HeH15 %A He, Wei %A Herrmann, Alexander %B CS2@HiPEAC %D 2015 %E Pimentel, Andy D. %E Wong, Stephan %E Pelosi, Gerardo %E Koren, Israel %E Agosta, Giovanni %E Barenghi, Alessandro %I ACM %K dblp %P 39-42 %T Placement Security Analysis for Side-Channel Resistant Dual-Rail Scheme in FPGA. %U http://dblp.uni-trier.de/db/conf/hipeac/cs2015.html#HeH15 %@ 978-1-4503-3187-6

@inproceedings{conf/hipeac/HeH15, added-at = {2018-11-06T00:00:00.000+0100}, author = {He, Wei and Herrmann, Alexander}, biburl = {https://www.bibsonomy.org/bibtex/270343820323f0f32b073fabd2b993d1e/dblp}, booktitle = {CS2@HiPEAC}, crossref = {conf/hipeac/2015cs}, editor = {Pimentel, Andy D. and Wong, Stephan and Pelosi, Gerardo and Koren, Israel and Agosta, Giovanni and Barenghi, Alessandro}, ee = {https://doi.org/10.1145/2694805.2694813}, interhash = {de15e466014b5610c90d1dda791c2957}, intrahash = {70343820323f0f32b073fabd2b993d1e}, isbn = {978-1-4503-3187-6}, keywords = {dblp}, pages = {39-42}, publisher = {ACM}, timestamp = {2018-11-07T16:31:46.000+0100}, title = {Placement Security Analysis for Side-Channel Resistant Dual-Rail Scheme in FPGA.}, url = {http://dblp.uni-trier.de/db/conf/hipeac/cs2015.html#HeH15}, year = 2015 }