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%0 Conference Paper
%1 conf/ddecs/RavottoSR10
%A Ravotto, Danilo
%A Sánchez, Ernesto
%A Reorda, Matteo Sonza
%B DDECS
%D 2010
%E Gramatová, Elena
%E Kotásek, Zdenek
%E Steininger, Andreas
%E Vierhaus, Heinrich Theodor
%E Zimmermann, Horst
%I IEEE Computer Society
%K dblp
%P 289-292
%T A hardware accelerated framework for the generation of design validation programs for SMT processors.
%U http://dblp.uni-trier.de/db/conf/ddecs/ddecs2010.html#RavottoSR10
%@ 978-1-4244-6612-2
@inproceedings{conf/ddecs/RavottoSR10,
added-at = {2023-03-24T00:00:00.000+0100},
author = {Ravotto, Danilo and Sánchez, Ernesto and Reorda, Matteo Sonza},
biburl = {https://www.bibsonomy.org/bibtex/22c2407ed180ecbb7884e583c5e097c96/dblp},
booktitle = {DDECS},
crossref = {conf/ddecs/2010},
editor = {Gramatová, Elena and Kotásek, Zdenek and Steininger, Andreas and Vierhaus, Heinrich Theodor and Zimmermann, Horst},
ee = {https://www.wikidata.org/entity/Q60245856},
interhash = {dfde0c707aa439d05d5f05fdc0e8fed8},
intrahash = {2c2407ed180ecbb7884e583c5e097c96},
isbn = {978-1-4244-6612-2},
keywords = {dblp},
pages = {289-292},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T06:41:36.000+0200},
title = {A hardware accelerated framework for the generation of design validation programs for SMT processors.},
url = {http://dblp.uni-trier.de/db/conf/ddecs/ddecs2010.html#RavottoSR10},
year = 2010
}