%0 Journal Article %1 journals/ett/RaviSR21 %A Ravi, V. %A Singh, Shivendra %A Reka, S. Sofana %D 2021 %J Trans. Emerg. Telecommun. Technol. %K dblp %N 1 %T Memristor-based 2D1M architecture: Solution to sneak paths in multilevel memory. %U http://dblp.uni-trier.de/db/journals/ett/ett32.html#RaviSR21 %V 32

@article{journals/ett/RaviSR21, added-at = {2023-01-20T00:00:00.000+0100}, author = {Ravi, V. and Singh, Shivendra and Reka, S. Sofana}, biburl = {https://www.bibsonomy.org/bibtex/2cbe075f19238d43e2d842baef2e1391b/dblp}, ee = {https://doi.org/10.1002/ett.4143}, interhash = {dfe4159dcc871f59bcab3d5e08e0c19a}, intrahash = {cbe075f19238d43e2d842baef2e1391b}, journal = {Trans. Emerg. Telecommun. Technol.}, keywords = {dblp}, number = 1, timestamp = {2024-04-08T21:49:38.000+0200}, title = {Memristor-based 2D1M architecture: Solution to sneak paths in multilevel memory.}, url = {http://dblp.uni-trier.de/db/journals/ett/ett32.html#RaviSR21}, volume = 32, year = 2021 }