%0 Conference Paper %1 conf/vlsid/SahaSS15 %A Saha, Partha Pratim %A Saha, Sumonto %A Samanta, Tuhina %B VLSID %D 2015 %I IEEE Computer Society %K dblp %P 447-451 %T Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#SahaSS15 %@ 978-1-4799-6658-5

@inproceedings{conf/vlsid/SahaSS15, added-at = {2023-03-24T00:00:00.000+0100}, author = {Saha, Partha Pratim and Saha, Sumonto and Samanta, Tuhina}, biburl = {https://www.bibsonomy.org/bibtex/2210062bb4e1abd7323caac0864f096dd/dblp}, booktitle = {VLSID}, crossref = {conf/vlsid/2015}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2015.81}, interhash = {e47540c847722f35304288a532f0f3df}, intrahash = {210062bb4e1abd7323caac0864f096dd}, isbn = {978-1-4799-6658-5}, keywords = {dblp}, pages = {447-451}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:03.000+0200}, title = {Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#SahaSS15}, year = 2015 }