%0 Journal Article %1 journals/jssc/PiloABBCCL03 %A Pilo, Harold %A Anand, Darren %A Barth, John %A Burns, Steve %A Corson, Phil %A Covino, Jim %A Lamphier, Steve %D 2003 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1974-1980 %T A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. %U http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#PiloABBCCL03 %V 38

@article{journals/jssc/PiloABBCCL03, added-at = {2022-04-20T00:00:00.000+0200}, author = {Pilo, Harold and Anand, Darren and Barth, John and Burns, Steve and Corson, Phil and Covino, Jim and Lamphier, Steve}, biburl = {https://www.bibsonomy.org/bibtex/22564054541487592de6e85eaddb7277c/dblp}, ee = {https://doi.org/10.1109/JSSC.2003.818141}, interhash = {e66cd3008dc25d43990f2b8cccd14d99}, intrahash = {2564054541487592de6e85eaddb7277c}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1974-1980}, timestamp = {2024-04-08T10:43:01.000+0200}, title = {A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#PiloABBCCL03}, volume = 38, year = 2003 }