%0 Conference Paper %1 conf/vlsid/SainiAVS10 %A Saini, Sandeep %A Adimulam, Mahesh Kumar %A Veeramachaneni, Sreehari %A Srinivas, M. B. %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 411-416 %T An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#SainiAVS10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/SainiAVS10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Saini, Sandeep and Adimulam, Mahesh Kumar and Veeramachaneni, Sreehari and Srinivas, M. B.}, biburl = {https://www.bibsonomy.org/bibtex/2a16bc298bd0de26a8bfd1682ba47406e/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.53}, interhash = {edf85f7a42330f94fc43159494ca9e1d}, intrahash = {a16bc298bd0de26a8bfd1682ba47406e}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {411-416}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:37.000+0200}, title = {An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#SainiAVS10}, year = 2010 }