%0 Conference Paper %1 conf/aspdac/WuSJQ17 %A Wu, Yi %A Shen, Chuyu %A Jia, Yi %A Qian, Weikang %B ASP-DAC %D 2017 %I IEEE %K %P 163-169 %T Approximate logic synthesis for FPGA by wire removal and local function change. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2017.html#WuSJQ17 %@ 978-1-5090-1558-0

@inproceedings{conf/aspdac/WuSJQ17, added-at = {2023-12-14T15:53:37.000+0100}, author = {Wu, Yi and Shen, Chuyu and Jia, Yi and Qian, Weikang}, biburl = {https://www.bibsonomy.org/bibtex/272d1f1386bf7fbb593f23ea0b9420442/admin}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2017}, ee = {https://doi.org/10.1109/ASPDAC.2017.7858314}, interhash = {f0db03b7115f2d30a6695b5b48d561b1}, intrahash = {72d1f1386bf7fbb593f23ea0b9420442}, isbn = {978-1-5090-1558-0}, keywords = {}, pages = {163-169}, publisher = {IEEE}, timestamp = {2023-12-14T15:53:37.000+0100}, title = {Approximate logic synthesis for FPGA by wire removal and local function change.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2017.html#WuSJQ17}, year = 2017 }