%0 Journal Article %1 journals/tvlsi/LiuW15 %A Liu, Bao %A Wang, Lu %D 2015 %J IEEE Trans. Very Large Scale Integr. Syst. %K %N 9 %P 1577-1590 %T Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#LiuW15 %V 23

@article{journals/tvlsi/LiuW15, added-at = {2023-12-14T16:19:47.000+0100}, author = {Liu, Bao and Wang, Lu}, biburl = {https://www.bibsonomy.org/bibtex/21baadcf54e8de1d4f08bc8ee0ba8e5f4/admin}, ee = {https://doi.org/10.1109/TVLSI.2014.2352937}, interhash = {f66c540f1a6e40bf271359138f174644}, intrahash = {1baadcf54e8de1d4f08bc8ee0ba8e5f4}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {}, number = 9, pages = {1577-1590}, timestamp = {2023-12-14T16:19:47.000+0100}, title = {Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#LiuW15}, volume = 23, year = 2015 }