%0 Conference Paper %1 conf/fpl/LiuPBC14 %A Liu, Junyi %A Peyrl, Helfried %A Burg, Andreas %A Constantinides, George A. %B FPL %D 2014 %I IEEE %K dblp %P 1-8 %T FPGA implementation of an interior point method for high-speed model predictive control. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#LiuPBC14

@inproceedings{conf/fpl/LiuPBC14, added-at = {2024-05-07T00:00:00.000+0200}, author = {Liu, Junyi and Peyrl, Helfried and Burg, Andreas and Constantinides, George A.}, biburl = {https://www.bibsonomy.org/bibtex/2f53929a6c913a15017e3c160dff0caa0/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2014}, ee = {https://doi.org/10.1109/FPL.2014.6927473}, interhash = {f9e6368894c9d83607e7cc4cc22aa6bd}, intrahash = {f53929a6c913a15017e3c160dff0caa0}, keywords = {dblp}, pages = {1-8}, publisher = {IEEE}, timestamp = {2024-05-13T09:28:16.000+0200}, title = {FPGA implementation of an interior point method for high-speed model predictive control.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#LiuPBC14}, year = 2014 }