%0 Journal Article %1 journals/tcad/WangGYLXZ17 %A Wang, Chao %A Gong, Lei %A Yu, Qi %A Li, Xi %A Xie, Yuan %A Zhou, Xuehai %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 3 %P 513-517 %T DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#WangGYLXZ17 %V 36

@article{journals/tcad/WangGYLXZ17, added-at = {2020-09-24T00:00:00.000+0200}, author = {Wang, Chao and Gong, Lei and Yu, Qi and Li, Xi and Xie, Yuan and Zhou, Xuehai}, biburl = {https://www.bibsonomy.org/bibtex/28682be9512e3ad4c813758c802b28606/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2587683}, interhash = {fcdb41d63ac7aeda62dfbe01ff439bf7}, intrahash = {8682be9512e3ad4c813758c802b28606}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 3, pages = {513-517}, timestamp = {2020-09-25T11:48:28.000+0200}, title = {DLAU: A Scalable Deep Learning Accelerator Unit on FPGA.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#WangGYLXZ17}, volume = 36, year = 2017 }