%0 Conference Paper %1 conf/dac/WeninVCLG89 %A Wenin, Jacques %A Verhasselt, Johan %A Camp, Marc Van %A Leonard, Jean %A Guebels, Pierre %B DAC %D 1989 %E Thomas, Donald E. %I ACM Press %K dblp %P 662-667 %T Rule-based VLSI Verification System Constrained by Layout Parasitics. %U http://dblp.uni-trier.de/db/conf/dac/dac89.html#WeninVCLG89

@inproceedings{conf/dac/WeninVCLG89, added-at = {2017-03-16T00:00:00.000+0100}, author = {Wenin, Jacques and Verhasselt, Johan and Camp, Marc Van and Leonard, Jean and Guebels, Pierre}, biburl = {https://www.bibsonomy.org/bibtex/252ee855c2c9bb1dfbc3b53252c6f71ec/dblp}, booktitle = {DAC}, crossref = {conf/dac/1989}, editor = {Thomas, Donald E.}, ee = {http://doi.acm.org/10.1145/74382.74499}, interhash = {fe3fe7fe8727b473171b0017ac209a53}, intrahash = {52ee855c2c9bb1dfbc3b53252c6f71ec}, keywords = {dblp}, pages = {662-667}, publisher = {ACM Press}, timestamp = {2017-03-17T11:39:10.000+0100}, title = {Rule-based VLSI Verification System Constrained by Layout Parasitics.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac89.html#WeninVCLG89}, year = 1989 }