%0 Journal Article %1 journals/tse/ParnasC86 %A Parnas, David Lorge %A Clements, Paul C. %D 1986 %J IEEE Trans. Software Eng. %K dblp %N 2 %P 251-257 %T A Rational Design Process: How and Why to Fake it. %U http://dblp.uni-trier.de/db/journals/tse/tse12.html#ParnasC86 %V 12

@article{journals/tse/ParnasC86, added-at = {2015-12-10T00:00:00.000+0100}, author = {Parnas, David Lorge and Clements, Paul C.}, biburl = {https://www.bibsonomy.org/bibtex/23e11b1ed869846a0e2cd032363263de3/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TSE.1986.6312940}, interhash = {07e3c942d8bc06cdcd8cb5ac3590258e}, intrahash = {3e11b1ed869846a0e2cd032363263de3}, journal = {IEEE Trans. Software Eng.}, keywords = {dblp}, note = {Correction: IEEE Trans. Software Eng. 12(8): 874 (1986)}, number = 2, pages = {251-257}, timestamp = {2015-12-12T11:55:27.000+0100}, title = {A Rational Design Process: How and Why to Fake it.}, url = {http://dblp.uni-trier.de/db/journals/tse/tse12.html#ParnasC86}, volume = 12, year = 1986 }